VHDL is a versatile and powerful hardware description language which is useful for modeling digital systems at various levels of design abstraction. This language is for describing the structural, physical and behavioral characteristics of digital systems. Execution of a VHDL program results in a simulation of the digital system allows us to validate the design prior to fabrication of Digital Integrated circuit. This practical introduces basic on VHDL concepts and constructs. It introduces the VHDL from simulation cycle to synthesis level in combinational and sequential circuits.
Very Large Scale integration technology, when especially used for digital integrated circuit design, is mandatory the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware fabrication in the foundry (gates and wires). Hardware Description Language (HDL) allows designs to be described using any methodology - top down, bottom up or middle out. VHDL can be used to describe hardware at the gate level or in a more abstract way. This course is to introduce the digital system design concepts through hardware description Language, VHDL programming, design flow of VLSI, and architectures of CPLD and FPGA. It is mainly aimed at design of combinational and sequential functions at gate / behavioral level and simulates and verifies their functionality using the Hardware description Language (VHDL)